1. Field of the Invention
The present invention generally relates to a method and apparatus for monitoring and testing electro-migration (EM) and time dependent dielectric breakdown (TDDB), and more particularly to a method and apparatus for addressable wiring test array formed using only back-end-of-the-line (BEOL) metal wiring levels.
2. Description of the Related Art
Generally, two types of tests are conducted on the metal wiring of a chip. The first one is called TDDB (time dependent dielectric breakdown), and the second one is the EM (electro-migration) test.
The purpose of TDDB test is to find out whether the quality of the insulator used for the BEOL (back-end-of-the-line) meets specifications. This test is done by stressing metal wiring in the BEOL at different voltages. One example is to apply a voltage ranged between 5 and 35 volts on the testing metal wire and the adjacent probing metal wire. The time required for electrical breakdown of the insulator is measured and recorded. In some cases, the voltage applied is slightly less than the intrinsic breakdown strength of the insulator. In other cases, tests are done below 12.5 volts. A successful test is usually defined by no breakdown up to 1000 hours of stressing. This means that the leakage current is below 10−6 A during the whole test period.
On the other hand, the purpose of electro-migration (EM) stressing is to determine if a conducting line can carry a predetermined amount of current without an electrical opening being created in the line by current induced diffusion of the conducting material. With this test, a high current density e.g. 16 m Å/um is driven through a single test line at certain temperature, e.g. 295° C., and the time, e.g. 200 hours, for an electrical open to be created is measured. As long as this time is longer than required by usage requirements, then the test is considered successful. For an EM test, the shorts to the adjacent probing wiring are also recorded. To ensure high metal wiring quality, it is demanded that metal in the BEOL passes these two tests.
Electro-migration has long been identified as the major metal failure mechanism. It is one of the worst reliability concerns for very-large-scale-integration (VLSI) manufacturing since 1960. The problem not only needs to be overcome during fabrication period in order to qualify the process, but it also persists through the lift time of the chip. Voids are created inside of the metal conductors due to metal ion movement caused by high density of current flow.
In short, electro-migration failure is caused by a positive divergence of the ionic flux leads to an accumulation of vacancies, forming void in the metal. It appears that ions are moved “downstream” by the force of “electron wind”. Electro-migration and its related failures therefore can be categorized as a wear-out mechanism. In general, the failure rate is proportional to current density and the surrounding temperature.
The EM problem becomes worse as the feature sizes both in width and thickness of metal wirings are further scaled. The current density can easily exceed 1E5 amps/cm 2 for wires with lack of sufficient cross-sectional area. It was observed, when metal lines cross over steep corners with topology tend to be thinner than normal. These corner regions as well as via structures are the most common locations for EM to take place. Proposed methods to slow down the EM effect including: (1) adding copper (0.5-4%) into Al film, (2) adding Ti (0.1-0.5%) into the Al film, (3) using CVD tungsten metal studs (4) using diffusion barrier liners, etc.
Several conventional methods to monitor and test electro-migration and TDDB have been developed. Certain exemplary conventional methods are described below.
Acceleration EM tests carried out using high current, voltage and temperature stress can screen out the defective chips in a relative short period of time. Several methods have been proposed to teach how to conduct such EM test.
A method to measure EM effect uses an EM sensor having a poly-silicon body, a monitored metal piece, and two electrodes. The electrodes are used to probe the connectivity of an EM sensor built by using an intrinsic poly-silicon element. A long metal that is placed on top of the sensor is stressed by a high voltage. When EM mechanism occurs within the metal, the resulting local joule heating will cause the mobility of the senor to drastically increase. This is an indirect measurement of EM. It doesn't test metal with topology with corners and via contact regions. It fails to locate the open/short defects. Furthermore, it requires a poly-silicon layer, which means more process steps and is thus more expensive to make the test macro.
An alternative method to test metal wirings is to directly measure the resistance of a test structure formed by metal wiring. Such a test structure is designed to measure wire resistance in terms of voltage drop after a period of high-voltage and high-temperature stress. This test structure is used to check EM failure and time dependent dielectric breakdown (TDDB) via one metal level. It cannot, however, position the open/short defect location, nor can it count the number of defects in the test macro. Therefore, this method provides very little information about the metal defects.
A similar test structure has been commonly used for the TDDB test in the semiconductor. This test macro includes a long (totally 8 meters) serpentine wirings having minimum ground rule pitch with hundreds of turns and corners. Like the previous method, this method further includes two probing wires Comb-B and Comb-A, which are used to detect the dielectric break down where metal short occurs. For process debugging during development period, it is critical that defect locations can be presented so that failure analysis can be conducted. For such design, however, it is not possible to provide defect locations.
Another alternative conventional method tests metal interconnects containing a plurality of metal segments connected together with vias. The structure is more close to the real life interconnects. The resistance of the test structure is compared to a control structure which is less prone to failure. If the resistance deviation between test and control structures exceeds a certain level, the part fails the test and is then rejected. This is a more direct measurement of EM.
However, all the conventional test methodologies proposed so far can not provide open/short defect address. They may be used to qualify the BEOL process, but it will not be easy for the engineer to spot the defect and zoom in to conduct failure analysis.